FPGA Design
Signal Processing, DFE, 5G O-RAN RU
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Azcom highly experienced team offers FPGA design services across all the major device families. Covering the complete development process, from architecture definition to RTL code development, simulation and testing, we support customers to solve their design challenges in different application domains.
We have major experience in signal processing, complex DFEs design and 5G RU FPGA firmware development.
Design Services
- FPGA design services on major FPGA device families (Xilinx, Intel and Lattice).
- Full development process ranging from architecture definition to RTL code development, simulation and testing
- Customer guidance in FPGA device selection
- High speed interface implementation and last generation high complexity IP integration
- Finite precision processing simulation fully aligned with RTL FPGA code implementation
- Design migration to latest devices
- ASIC to FPGA conversion for device prototyping and cost effective early design validation
Key Differentiators
- Adoption of new technologies such as the Xilinx Zynq®-7000 and Intel SoCs (Programmable SoC) to reduce time to market
- Design experience involving multiple clocks domains and high frequency architectures
- Solving congested logic load designs issues in term of timing constraints and best logic cells allocations
- High performance designs based on large degree of parallelism and pipelining
- Optimized digital processing architecture mapping for high complexity algorithm implementation
- MATLAB finite precision processing chain and simulation to shorten development time, enabling early performance evaluation and enforcing solution validation
Signal Processing, DFE, 5G O-RAN RU
Azcom engineering team has consolidated expertise in signal processing domain, complex DFEs design and O-RAN 5G RU development. These systems make extensive use of FPGA technology to accelerate performance demanding functional blocks, on which Azcom has a consolidated implementation experience.
Some key examples are:

O-RAN 5G RU – Low PHY, CPRI, eCPRI, U/C plane function, eCPRI M/S plane and O&M on SoC FPGA processor cores.

Radio Digital Up and Down conversion chains (interpolators & decimators, shaping filters, CFR, FFT/IFFT, NCO/CORDIC, digital modulation / demodulation)

Coding/decoding (block, convolutional Viterbi and Turbo)

Channel equalization

Latest generation power amplifier Digital Pre-distortion algorithms

Matrices manipulations (pseudoinverse, least squares, linear system solver, Cholesky, QR decomposition)

Fixed-point precision adaptation strategy on FPGA
References

4G UE PHY stack
4G UE PHY stack

5G RU DFE Conversion Chains
5G RU DFE Conversion Chains

4G/5G O-Ran 7.2 Low-Phy Offload
4G/5G O-Ran 7.2 Low-Phy Offload

Multi-Antenna/Carriers/Bands Crest Factor Reduction
Multi-Antenna/Carriers/Bands Crest Factor Reduction

L1 BaseBand Modulation/Demodulation Chains
L1 BaseBand Modulation/Demodulation Chains

High Performance MMSE Digital Predistortion Algorithms
High Performance MMSE Digital Predistortion Algorithms

Multi standard flexible CPRI antenna I/F
Multi standard flexible CPRI antenna I/F
Platform Expertise


